This invention relates generally to divider circuits, and more particularly to high speed divide-by-N/N+1 prescaler circuit.
Prescaler circuits for use in high speed dividers, frequency synthesizers, and the like are well known. A dual modulus prescaler is a counter whose division ratio can be switched from one value to another by an external control signal. That is, the prescaler can divide by first factor when the applied control signal is high, or by a second factor when the applied control sign is low. An in-depth discussion of prescalers can be found in "Phase-Locked Loops" by Dr. Ronald E. Best, copyright 1984, MacGraw-Hill Inc.
In an article entitled "A 250 MHz Dynamic CMOS Dual Modulus (.div.8/9) Prescaler" by Chris Groves et al., and beginning on page 110 of the minutes of the 1984 Conference on Advanced Research in VLSI, MIT, there is described a dual modulus (.div.8/9) prescaler for use in a digital 250 MHz CMOS programmable divider circuit. This prescaler comprises three cascaded standard CMOS inverters, one NOR gate, and three functionally distinct inverter circuits. Unfortunately, the circuit operates in a primarily sequential manner thus limiting its speed. Furthermore, use of a significant number of components further restricts speed and increases the circuit's power consumption.
In an effort to overcome this, U.S. Pat. application Ser. No. 300,449 filed Jan. 23, 1989 entitled "High Speed Prescaler" and assigned to the assignee of the present invention describes a high speed CMOS divide by 4/5 prescaler circuit including first, second, third, fourth, and fifth inverter stages. When a modulus control signal is high, the prescaler operates as five clocked inverters in series having an output which is fed back to the input of the initial stage. That is, the circuit operates as a five stage clocked ring oscillator wherein only one output changes on each clock edge. When a modulus control signal is low indicating that a divide by four is desired, the counter operates as a five stage ring oscillator for seven clock edges. On the eighth edge, feed forward circuitry forces the last three stages to change states simultaneously. While this circuit utilized fewer components and exhibited greater speed, the construction of a larger prescaler prim (e.g., a divide by 32/33) would require a large number of stages each of which would have to operate at high frequency and resulting in the consumption of a great deal of power.